EE Seminar: Improving Prediction of Subroutine Return Branches
Speaker: Netanel Buhbut,
M.Sc. student under the supervision of Prof. Shlomo Weiss
Monday, February 13th, 2017 at 15:00
Room 011, Kitot Bldg., Faculty of Engineering
Improving Prediction of Subroutine Return Branches
Abstract
This work studies the return from subroutine in deeply pipelined VLIW DSP. Modern DSPs are designed to be deeply pipelined, some in order of 15 and up, to cope with high clock frequencies. Speculative instructions enter the processor's pipeline to avoid pipeline stalls and keep high throughput. This work proposes a fast and simple return from subroutine prediction using Return-Address Stack (RAS) and Return-Address Buffer (RAB). The proposed technique was measured using the output trace of a SimpleScalar simulator running a subset of Mediabench and Coremark benchmarks. While investigating the return from subroutine, we found a pairing mismatch in the benchmarks. In this work, the pairing mismatch is defined and a recovery mechanism, that helps the RAS recover from data corruption, is described. Finally, the design was synthesized for FPGA, in order to determine if it is a feasible solution for modern DSPs in terms of core frequency, power and area.
