Digital Verification Engineer SoC-Automotive

Requirements

• B.Sc. in Electronic Engineering MSc. an advantage
• At least 3 years’ experience as verification engineer. Completing full development cycle an advantage.
• Knowledge in verification methodologies, tools (simulators, coverage tools, etc.), and techniques
•  Knowledge of Verilog, System Verilog or Specman
•  Experience in Python / Perl programming
• Good knowledge of UNIX environment
• Developing UVM based verification environments an advantage.
• Experience emulation, Formal an advantage
• Self-motivated and self-directed, proactive
• Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization
• Ability to troubleshoot and analyze complex problems