Verification Engineer
חברה:
Samsung
מיקום משרה:
תל אביב
תיאור משרה:
Samsung R&D center is looking for Verification Engineer to join our team.
Samsung (SIRC), shaping the world of tomorrow, Today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology.
Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion.
דרישות משרה:
Responsibilities include:
- Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage
- Create a constrained-random verification environment using UVM.
- Work closely with architecture & Design teams.
- Initiate and implement flow and environment improvements to scale with growing project complexity.
- Work closely with Verification teams to enable smooth execution and high quality.
Requirements
- BSc/ MSc in Electrical Engineering or Computer Science
- At least 2 years of experience in verification
- Knowledge in design and verification tools and methodologies
- Knowledge of Verilog, System Verilog or Specman.
- Knowledge in Unix-based environments.
- Methodological approach to building of verification environment and test plan.
- Capable of taking responsibility for various Verification tasks and bringing them to successful implementation.
- Excellent communication and problem-solving skills.
- Thinks outside the box - finds creative solutions for complicated tasks.
Advantages
Experience with UVM Experience in AI Hardware Acceleration industry Experience with Python
היקף משרה:
מלאה
מתאים ל:
בוגרים
מועד אחרון להגשת מועמדות:
שישי, דצמבר 3, 2021 - 12:30
