3.1.15 Seminar by Zvi Lupo

You are invited to attend a lecture

by

Zvi Lupu

(MSc. student under the supervision of Prof. Eran Socher)

School of Electrical Engineering, Tel-Aviv University, Tel-Aviv 69978, Israel

Column-Parallel Single-Slope ADC for Infrared Image Sensor applications

In recent years, the requirements of infrared sensors, and more specifically, uncooled IRFPAs are increasing intensively. Main requirements are frame rate, noise, dynamic range and resolution. With IRFPAs requirements going toward more integrated, more functional and more micro-system, readout circuit bandwidth needs to increase in order to keep the same frame rate for increase arrays size. For example, array of 400 X 300 (120,000 pixels) with a frame rate of 240Hz will require pixel rate of ~29MHz. for application with that readout speed, high-speed analog-to-digital converter (ADC) is require. In addition to speed, for a high performance ADC this can poses a design challenge. Due to that on-chip ADC is required. Adding the ADC in the chip will decrease system complexity and will simplify the interface.

Many sensors employ single slope column-parallel ADCs. Although single slope architecture has a disadvantage of having slow conversion rate, it has the advantages of having a very simple implementation with minimal analog content, low gain and offset errors as well as being highly linear. Compared to a global ADC, this approach required lower bandwidth in readout circuit (for each column) and can affords lower power operation.

In this work, single-slope ADC architecture was chosen and implemented. Experimental results show that the ADC is highly linear, with 11.3 bits ENOB and with SNR of 69.5dB that consume 26µW. in addition, digital summing theoretical justification was presented and shown that by averaging 4 samples, the resolution increases by 1bit but when introducing high input noise as dither to the ADC, the result of 4 sample summation is highly resemble (98%) to a 2 bit resolution increase.

Sunday, March 1, 2015, at 10:00

Room 001, Computer and Software Engineering building