30.4.15
You are invited to attend a lecture
By
Lev Merensky
PhD student under the supervision of Prof. Doron Shmilovitz1 and Dr. Amit S. Kesar2
- School of Electrical Engineering, Tel-Aviv University, Tel-Aviv 69978, Israel
- Applied Physics Division, Soreq Nuclear Research Center, Yavne, Israel
Nanosecond and Sub-nanosecond
Pulsed Power Circuits
Drift step recovery diodes (DSRDs) and silicon avalanche shaper (SAS) diodes are semiconductor devices that can be combined to generate high-voltage pulses in the sub-nanosecond regime. The circuit topology that drives the DSRD and the SAS plays a major role in the performance of a pulsed power generator. A comprehensive study that was conducted to improve the performance of sub-nanosecond pulsed power generators is presented. The study achieved three major objectives: The first objective was to quantify the efficiency of the pulsed power generator and map its major loss mechanisms. The second objective was to enhance the circuit performance by driving the DSRD with a preliminary DSRD compression stage. The final objective was to experimentally determine the conditions for driving the SAS.
The efficiency study combined experiments and simulations to characterize the conduction losses in the switching devices. The major achievement of the study was the development of a trade-off map for a case-study circuit that allows for the selection of the desired compromise between efficiency and pulse performance parameters. The case-study circuit produced up to 2.2 kV at a pulse repetition frequency (PRF) of up to 1 MHz. This high-PRF capability provides a significant motivation for the effort to improve efficiency.
With regard to the second objective, we report the enhanced performance that was achieved by using a cascaded-compression method to produce a high-voltage nanosecond pulse. The pulse that was driven by this method was sharpened by a fast avalanche diode. A 6-kV, 130-ps-rise-time circuit, with a rise rate exceeding 40 kV/ns, is presented. The presented topology demonstrates two novel advancements in the design of pulse-forming circuits. The first development is the timing together, and combining the outputs of two preliminary nanosecond compression stages. The second achievement is the successful cascaded driving of a DSRD by the preliminary DSRD-based compression stage.
In pursuit of the third objective, a dedicated circuit was used to drive the SAS diode over a wide range of peak voltages and rise times. The study revealed the limits on the minimal conditions required to achieve an avalanche effect that can sharpen the DSRD pulse from the nanosecond scale to the 100-ps scale. Additionally, the study investigated the limits on the minimal time between two pulses, which, in turn, imply physical limits on the PRF.
Thursday, April 30, 2015, at 11:00
Room 011, Kitot building
