Kfir Twizer- CW Radar-Based Road Environment Detection and Matching for Robust Localization in GNSS-denied scenarios

סמינר מחלקת מערכות - EE Systems Seminar

28 בינואר 2024, 15:00 
Electrical Engineering-Kitot Building 011 Hall  
Kfir Twizer- CW Radar-Based Road Environment Detection and Matching for Robust Localization in GNSS-denied scenarios

 

Electrical Engineering Systems Seminar

 

Speaker: Kfir Twizer

M.Sc. student under the supervision of Prof. Ben-Zion Bobrovsky

 

Sunday, 28th January 2024, at 15:00

Room 011, Kitot Building, Faculty of Engineering

 

FMCW Radar-Based Road Environment Detection and Matching for Robust Localization in GNSS-denied scenarios

 

Abstract

Real-time global localization information is a critical component in modern navigation and perception systems, as it enables effective navigation, route planning and environment awareness. During GNSS outages, or under poor signal conditions, other complementary sources are employed. State-of-the-art techniques often use camera and/or LiDAR sensors to perform this task. However, these sensors performance is vulnerable to adverse weather conditions like rain, fog or snow. In such scenarios, Radars emerge as reliable primary sensors, aligning with the redundancy requirements of the automotive industry.

In this work, we propose a robust and efficient model for radar-based self-localization in urban roads. Our model extract relevant information for navigation from radar measurements; stationary obstacles along-side roads are detected and tracked through an enhanced version of extended target tracking framework developed in this work; Road users' movement in the range of interest is detected as well. This information is then matched to different classes of HD semantic maps using an innovative map-matching algorithm developed in this study, which integrates Likelihood Fields. Ego pose is being estimated over time according to the map-matching score.

Our model eliminates the need for pre-generated custom occupancy grid maps, known for their maintenance challenges, non-availability and storage costs. Instead, it seamlessly integrates with widely used semantic maps available today. Across diverse urban scenarios from the nuScenes public dataset, our model demonstrates a 1m/1.5m RMS lateral/longitudinal error correspondingly during typical periods of GNSS outage.

 

השתתפות בסמינר תיתן קרדיט שמיעה = עפ"י רישום שם מלא + מספר ת.ז. בדף הנוכחות שיועבר באולם במהלך הסמינר

 

 

 

ד"ר נמרוד גינזברג

ד"ר נמרוד גינזברג

 

Optical Engineer

Responsibilities

You’ll be joining the optics team

Chip Design Engineer

What you’ll be doing:

  • Work in a combined design and verification team that develops front-end design for the Switch silicon GPU and HCA.

  • Chip level integrations and connectivity.

  • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. Interaction with organization-wide groups.

 

What we need to see:

Chip Design Emulation Engineer

 

What you will be doing:

  • The main responsibility is emulation and prototyping of complex chip designs. This includes defining the methodology and crafting the infrastructure needed to quickly take large chips into hardware emulation platforms.

  • The job also requires close collaboration with design, verification, and software engineers to enable embedded software and application software development.

Chip Design Verification Engineer

What you'll be doing:

  • Work in a combined design and verification team which develops core units within the Networking silicon.

  • Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.

  • Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

 

What we need to see:

Formal Verification Engineer

 

What you'll be doing:

  • In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
  • You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of NVIDIA's core technology.

 

What we need to see:

IT Engineer

What you’ll be doing:

  • Provide best in class service level and compliance

  • Resolve hardware and software issues

  • Onboard new hires from IT aspect / offboard leaving employees

  • Laptops and Desktops installation/deployment

  • Document your efforts, tasks and activities (ticketing system) and assist in the creation and maintaining of all technical documentation

 

What we need to see:

Full Chip STA Engineer

What you will be doing:

  • Be in charge of full chip level STA convergence from early stages to signoff.

  • Take part in Full Chip floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.

  • Define and optimize, together with CAD, STA signoff flows and methodologies.

  • Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.

Physical Design Backend Engineer

What you will be doing:

  • Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

  • Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

עמודים

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