EE Seminar: BTB Design And Optimization For VLIW DSPs

~~Speaker: Oren Cohen, 
M.Sc. student under the supervision of Prof. ShlomoWiess

Wednesday, January 13, 2016 at 15:00
Room 011, Kitot Bldg., Faculty of Engineering

BTB Design And Optimization For VLIW DSPs

Abstract

The demand for high performance, low power and low cost devices is greater than ever. This is especially the case when referring to real time tasks such as audio and video decoding or encoding. One way to target these goals is by implementing academic ideas and theories. But this is quite difficult due to the fact that in most cases the gap between theoretical ideas and practical implementation is so big that neither the researcher nor the developer can see eye to eye. The researcher cannot examine his theoretical ideas in order to deduce feasibility and developers have no motivation to deal with academic ideas since from their point of view they are not mature enough.

This seminar will present new concept to mitigate branch penalties for VLIW DSPs, which was tested and analyzed on dedicated simulation platform.

The solution presented by our research is based on BTB design. BTB design is usually not associated with VLIW DSPs. The common mitigation for branches penalty in VLIW DSPs is static prediction, delayed branches or combination of both. Our research presents new approach based on BTB solution, which improves the VLIW DSP performance.