EE ZOOM Seminar: Hybrid Cache with Gain-Cell embedded-DRAM
השתתפות בסמינר תיתן קרדיט שמיעה = עפ"י רישום שם מלא + מספר ת.ז. בצ'אט
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https://us04web.zoom.us/j/2737782417?pwd=a0w3QjEvMWtaQlhMeFhxa1l0bkxPdz09
Meeting ID: 273 778 2417
Password: 4VdSzP
Speaker: Junyi Zhou
M.Sc. student under the supervision of Prof. Shlomo Weiss
Monday, June 8th, 2020 at 15:00
Hybrid Cache with Gain-Cell embedded-DRAM
Abstract
In typical embedded CPU, the on-chip storage is critical to meet high performance requirements and is desired to be large. However, the fast increasing size of the on-chip storage based on traditional SRAM cells, such as first level data (L1D) cache and register file (RF), makes the area cost and energy consumption unsustainable for future embedded applications.
In this paper, we propose to use the Gain-Cell embedded-DRAM (GC-eDRAM) as an alternative for the on-chip first level data (L1D) cache. In general, compared to SRAM conventional memory cells, GC-eDRAM (e.g. 2T1C) enables higher density and lower leakage power, but suffers from long data access latency and limited Data Retention Time (DRT). Periodic refresh operation is a viable approach to maintain data integrity but aggravates the performance and energy consumption with the scaling of eDRAM cells into low-power deep sub-micron technology nodes.
However, recent advancements in Gain-Cell embedded-DRAM technology enables fast data access and long DRT. In detail, we propose to replace the data array of the L1D cache with Gain-Cell eDRAM while keeping the conventional usage of SRAM in the tag array which takes up very small portion area-wise of the cache comparably.
The evaluation on our proposed hybrid L1D cache demonstrates that, comparing to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.
