EE Seminar: Design of a Decoupled Branch Predictor for a Deeply Pipelined Embedded VLIW DSP

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Speaker: Konstantin Berestizshevsky,
M.Sc. student under the supervision of Prof. Shlomo Weiss

Wednesday, May 25, 2016 at 15:00
Room 011, Kitot Bldg., Faculty of Engineering

Design of a Decoupled Branch Predictor for a Deeply Pipelined Embedded VLIW DSP
Abstract
One of the classical problems in the world of computer architecture is the ``branch prediction'' problem, also known as the "control hazard". This problem occurs whenever a pipelined processor fetches a branch instruction, making it unclear which instruction to fetch next. Waiting until the resolution of the branch in the deeper pipeline stages will cost several clock cycles, and hence an immediate branch-prediction should be made. Numerous DSP designs that relied on static (non-hardware) solutions of the branch-prediction problem began gradually loosing performance as their pipelines deepened, causing the penalties of branch mis-prediction to become unbearable.

This work presents a design of a dynamic branch predictor. The proposed design, called decoupled-predictor, literally decouples the prediction making from the prediction update stages of the scheme. This separation follows the basic rule of "divide and conquer", making it possible to tailor each part for its particular task. Moreover, such an approach leads the way to a successful micro-architectural planning, since the prediction and the update stages are naturally decoupled in the microprocessor's pipeline. In this thesis we combine the opportunity of developing a new branch prediction approach, with the opportunity of incorporating a dynamic branch prediction into a DSP core that formerly relied on a static prediction. This thesis presents a detailed description of the predictor architecture and evaluates its performance through a set of trace driven simulations. Finally, we address the cost efficiency of the design by offering memory saving optimizations.