EE Seminar: Lowering LDPC Error Floors Using Product Coding Schemes
Speaker: Guy Zohar
M.Sc. student under the supervision of Prof. Simon Litsyn
Wednesday, November 30th, 2016 at 15:30
Room 011, Kitot Bldg., Faculty of Engineering
Lowering LDPC Error Floors Using Product Coding Schemes
Abstract
Low-density parity-check codes are among the most powerful error correcting codes currently known, with their error floor being one of their main disadvantages.
Our research deals with ways to diminish the error floor phenomenon in these codes and thus allow for the design of a low error rate code. In our talk, we will present two coding schemes.
The first scheme, the Product Coding (PC) Scheme is a product code of an LDPC row code with a CRC for every row and a high rate erasure column code. The decoder performs column decoding and is able to correct a small number of erroneous rows and lower the error rate dramatically. The row error rate of the scheme is analyzed and is upper bounded to very low rates using low complexity computation. The encoding and decoding algorithms of the scheme are also given and the complexity of the decoding algorithm is discussed.
The second scheme, the Sub-Product Coding (SPC) Scheme, encodes only part of the columns and thereby achieves higher throughput and better complexity performance trade-off than the product coding scheme. We analyze the scheme in terms of complexity and row error probability and provide several methods for the design of this scheme under the AWGN channel. Finally, we analyze the asymptotic code performance over the BEC channel and provide lower and upper bounds on its error probability.
