EE Seminar: On massively multithreaded DSP architecture
Speaker: Ben Perach
M.Sc. student under the supervision of Prof. Shlomo Weiss
Wednesday, March 8th 2017 at 15:30
Room 011, Kitot Bldg., Faculty of Engineering
On massively multithreaded DSP architecture
Abstract
Processor designers attempt to gain performance by introducing new, more efficient architectures. Digital signal processors (DSP) are designed to process very efficiently digital signal applications. This focus allows DSP designers to select tradeoffs that may not be appropriate for general purpose processors. For example, typical power consumption of DSPs is measured in milliwatts while the power used by an Intel state-of-the-art processor is in the range of tens of watts. In recent years we have seen a growing use of GPUs by non-graphical scientific applications because of their computation capabilities.
In this work we introduce a new DSP architecture, designed on the basis of the same parallel processing principles used in GPU architectures.
We implement this new architecture on FPGA, show evaluation results for widely used DSP algorithms and evaluate die area and power consumption.
We achieve similar computation speeds as in GPUs, with reduced die area and power consumption due to the use of hardware adaptations for DSP applications.
