(The talk will be given in English)

Speaker:     Prof. Ido Tal

                                Electrical and Computer Engineering Department at Technion

Monday, June 24^th, 2024

12:00 - 13:00

Strong Polarization for Shortened and Punctured Polar Codes

Abstract

Polar codes were originally specified for codelengths that are powers of two. In many applications, it is desired to have a code that is not restricted to such lengths. Two common strategies of modifying the length of a code are shortening and puncturing. Simple and explicit schemes for shortening and puncturing were introduced by Wang and Liu, and by Niu, Chen, and Lin, respectively. In this paper, we prove that both schemes yield polar codes that are capacity achieving. Moreover, the probability of error for both the shortened and the punctured polar codes decreases to zero at the same exponential rate as seminal polar codes. These claims hold for all codelengths large enough.

Joint work with Boaz Shuval.

Short Bio

Ido Tal was born in Haifa, Israel, in 1975. He received the B.Sc., M.Sc., and Ph.D.\ degrees in computer science from Technion --- Israel Institute of Technology, Haifa, Israel, in 1998, 2003 and 2009, respectively. During 2010--2012 he was a postdoctoral scholar at the University of California at San Diego. In 2012 he joined the Electrical and Computer Engineering Department at Technion. His research interests include constrained coding and error-control coding. He received the IEEE Joint Communications Society/Information Theory Society Paper Award (jointly with Alexander Vardy) for the year 2017.

השתתפות בסמינר תיתן קרדיט שמיעה = עפ"י רישום שם מלא + מספר ת.ז. בטופס הנוכחות שיועבר באולם במהלך הסמינר

(The talk will be given in English)

Speaker:     Dr. Tzofnat Greenberg, SoC Architect at NVIDIA

Monday, June 24^th, 2024

12:00 - 13:00

Analog Processing-in-Memory of Deep Neural Networks

Abstract

Deep neural networks are usually executed by commodity hardware, mostly GPU platforms, and accelerators (such as Google's TPU), as they are compute and memory-intensive. In this talk, I will discuss the acceleration of DNNs using emerging memristive memory technologies, such as RRAM and STT-MRAM (also known as memristors). Memristors enable combining storage and computation on one physical entity. They enable computing an energy-efficient and highly parallel analog multiply-and-accumulate operation in-place, also known as processing-in-memory (PIM). To fulfill PIM’s potential, we consider hardware-based and algorithm-based approaches to accelerate DNNs.

First, we examine an on-chip training setup where an analog PIM-based accelerator supports DNNs' training and inference. Advanced optimization algorithms may only partially utilize the PIM module parallelism, leading to suboptimal hardware performance. In this study, we investigate and evaluate PIM implementations of (1) Stochastic gradient descent with momentum and (2) Quantize neural network (QNNs) training.

We also investigate an off-chip regime in which a pre-trained model is given and deployed to an analog PIM-based accelerator. Naively deploying a pre-trained model to the analog hardware will lead to significant accuracy degradation; therefore, we suggest the analog-aware post-training (APT) approach to calibrate the model to be more robust to analog noise. Our evaluation of several DNN models on the ImageNet dataset showed that our APT approach achieves similar accuracy as previous state-of-the-art analog-aware training methods, requiring less than 1% of the dataset to train and accelerating the noise adjustment time by up to 41X.

Short Bio

Tzofnat recently finished her Ph.D. under the supervision of Prof. Shahar Kvatinsky and Daniel Soudry. She is currently working as an SoC architect at NVIDIA.

השתתפות בסמינר תיתן קרדיט שמיעה = עפ"י רישום שם מלא + מספר ת.ז. בטופס הנוכחות שיועבר באולם במהלך הסמינר