EE Seminar: Fused-VIVT: Reducing Power by Coalescing the Cache Directory and TLB
Speaker: Eyal Naor
M.Sc. student under the supervision of Prof. Shlomo Weiss
Wednesday, April 10th, 2019 at 15:30
Room 011, Kitot Bldg., Faculty of Engineering
Fused-VIVT: Reducing Power by Coalescing the Cache Directory and TLB
Abstract
We propose a novel Fused-VIVT that merges the directories of the cache and TLB. The main benefit of this design is substantial power reduction in accessing cache directories, without readily affecting performance, area requirements and latency. When used in conjunction with a way-predictor, the energy consumption can be reduced by 90% compared to the traditional cache directory and TLB access scheme. The present research provides an evaluation of this proposal in these important aspects: energy consumption, area requirements, latency and performance. We also provide a comparison and analysis of a “traditional” micro-architecture consisting of a TLB and a physically tagged cache, with that of a Fused-VIVT. We also address various difficulties that could arise with implementing such a cache, including synonyms and coherency.
