EE Seminar: Parallel cycle-accurate systemC kernel

~~Speaker: Lior Ainey
M.Sc. student under the supervision of Prof. Shlomo Weiss

Wednesday, December 10th, 2014  at  15:30
Room 011, Kitot Bldg., Faculty of Engineering

Parallel cycle-accurate systemC kernel
   As hardware designs become more and more complex, the verification process takes longer. The bottleneck of verifying the design is the long period of time it takes to run simulations and especially long meaningful tests such as full System on Chip (SoC) simulations. Although multicore processors are now widely available, most of the simulators being used in the verification process are still unable to efficiently use multicore platforms. We developed and explored several techniques for efficiently distributing the design modules across multiple threads running in parallel. The focus was on implementing several approaches for parallelizing the simulator kernel and evaluating the performance of each approach.
    We presented two novel techniques for improving the parallel simulator kernel: one improves the overhead of thread parallelism by exploiting hardware simulation characteristics while the other improves task threading by collecting run-time statistics out of similar simulations. The result is a shorter simulation time and higher utilization ratio of the computing resources.
    The implementation is based on SystemCASS, which is a cycle accurate version of the SystemC simulator.

10 בדצמבר 2014, 15:30 
בניין כיתות חשמל, חדר 011 
EE Seminar: Parallel cycle-accurate systemC kernel
אוניברסיטת תל אביב עושה כל מאמץ לכבד זכויות יוצרים. אם בבעלותך זכויות יוצרים בתכנים שנמצאים פה ו/או השימוש
שנעשה בתכנים אלה לדעתך מפר זכויות, נא לפנות בהקדם לכתובת שכאן >>