You are invited to attend a lecture on Thursday, March ^9th, 2023, at 10:00

Room 011, Kitot Building

Frequency interleaved ADC Terabit CMOS Frontend

Aviad Haran

M.Sc. student under the supervision of Prof. Eran Socher

Abstract

With the advance of CMOS technology in the recent years fully integrating digital and analog circuits together into one IC has become feasible. The increase in operation speeds of the devices and clever design techniques have enabled CMOS to be used at frequencies well within the mm-wave regime. Cheap manufacturing, reduction in size, increased resolution and integratability are to name just a few of the incentives for venturing into such frequencies in CMOS. Among the many fields which have benefited from these recent advancements, Terabit ADCs—practical applications considered—these systems require large, multi-chip system and an expensive fabrication technology. A minimalist design of a sub-ADC in one of these analog frontends requires at the very least a linear wide band amplifier or buffer and some sort of interleaving mechanism such as down converting wide band mixers. 

Typically the performance of on-chip wide band amplifier or mixer at 100GHz frequencies is severely hindered by ICs interconnect; and the performance of the amplifier and mixer is limited by their output capacitance leading to the dominant corner frequency and breakdown restriction on the devices when delivering large signals. Recent research has shown promising results for bandwidth extension in CMOS, achieving over 20 GHz bandwidth using RF methods and techniques and a new approach for amplifiers utilizing inductive peaking which extend the bandwidth of a given circuit while allowing large enough devices to deliver current and voltage to a given load without breaking down devices with minimal spurs. However, whether these approaches can be merged into a analog frontend and used for frequency interleaving is yet to be seen.

Presented herein are the design process, measurements, and results of a new wideband mixer topology—a double balanced Gilbert cell using an active load with inductors to extend the bandwidth by peaking the output impedance mitigating output capacitance and down converting a 20GHz bandwidth signal to baseband. The scalability of the approach was demonstrated by fabricating a two sub-ADCs channel on a signal die to imitate a 40GHz FI-ADC frontend.

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